Since I don't have any background with FPGAs or Verilog, I'm setting up a list of goals I think I should accomplish before I set off to do anything more ambitious. Some of the goals won't have any links to specifics because I've started this blog after I started doing work with the FPGA.

Hardware interfacing goals Status Link
Strobe a pin at a specified duty cycle Done N/A
Transmit bytes @19200 to an RS232 terminal Done N/A
Receive bytes @ 19200 from RS232 terminal and display code on row of LEDs Done N/A
Receive a byte and then re transmit it. Done N/A
Generate timings to drive an SPI based LCD module Done View
Display a message on the LCD module and adjust its contrast Done N/A
Receive a byte from the serial port and display it on the LCD module In Progress View
Display a null terminated string of text stored in a ROM module on an RS232 terminal Done N/A
Read and write bytes to a 24LC64 and 24LC128 serial eeprom Not Started N/A
Set and read date and time with RTC module (demonstrates use of I2C bus) Not Started N/A
Read scan codes from PS2 keyboard and display codes onto RS232 terminal Not Started N/A
Send and receive bytes between FPGA and a PIC 16F917 using an 8bit wide tristate bus and two control pins Not Started N/A
System design goals Status Link
Implement and test a LIFO structure Done View
Implement and test an instruction fetch and decode unit for use with the stack processor In Progress View
Send and receive bytes between two modules on different clock domains using a FIFO Not Started N/A
Design a module that repeatedly displays a line of text on the RS232 terminal and use the timing analysis tools to determine how fast the circuit can be clocked before it breaks. Do testing to verify the timing results. Not Started N/A
Implement a 16bit stack machine. Memory map in rs232 module and LCD module. In Progress View
Write an assembler for the stack machine In Progress View
Combine all the modules from the previous goals into one system that demonstrates the functionality of each component. All modules should be memory mapped and controlled from code running on the stack machine. Afterwards do the timing analysis and verify that it works up to the maximum safe clock speed. Not Started N/A
fpga_simple.txt · Last modified: 2013/03/23 08:20 by millerb
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